INTELLIGENCE THATRUNS WHERE YOURPRODUCT LIVES
From training pipeline to deployed model on silicon — we own the full ML stack.
Ankh's AI/ML practice covers the complete arc from raw data to production inference: dataset curation and annotation, TensorFlow and PyTorch model development, INT8/INT4 quantization and pruning, TensorFlow Lite and ONNX Runtime deployment, hardware accelerator integration across Coral TPU, Hailo-8, NVIDIA Jetson, and Arm Ethos NPU, and the MLOps infrastructure that keeps models accurate after deployment.
What We Build
ML Training Pipeline Development
Data collection protocols, annotation tooling (Label Studio, CVAT, Roboflow), augmentation, training on AWS SageMaker or GCP Vertex AI, hyperparameter optimization with Optuna or Ray Tune, and MLflow or W&B experiment tracking — reproducible and version-controlled.
Edge Model Optimization & Deployment
Post-training quantization (INT8, INT4), quantization-aware training, structured and unstructured pruning, and knowledge distillation — validated against target hardware benchmarks: inference latency, peak SRAM, and energy per inference.
Computer Vision Model Development
Object detection (YOLOv8, YOLOv9, RT-DETR), semantic and instance segmentation, image classification, and anomaly detection — camera selection, dataset curation, NMS tuning, confidence calibration, and hardware accelerator integration.
Time-Series Anomaly Detection
LSTM sequence models, Transformer architectures with temporal attention, and autoencoder-based anomaly detectors — designed around stationarity characteristics, sampling rate, and memory constraints of the target platform.
Hardware Accelerator Integration
Model mapping to Coral Edge TPU, Hailo-8, Jetson Orin, Qualcomm AI Engine, CMSIS-NN, and Arm Ethos-U55/U85 — unsupported operator fallback or substitution with end-to-end inference validated against latency and power budgets.
MLOps Pipeline & Model Lifecycle Management
Automated MLOps pipelines monitoring confidence distributions for drift, triggering retraining at defined thresholds, versioning candidates via A/B evaluation, and gating deployment through CI/CD accuracy and latency regression tests.
Federated Learning for Privacy-Preserving Edge AI
Federated training with TensorFlow Federated and Flower — secure aggregation, non-IID data distribution across device populations, and differential privacy noise where regulatory requirements demand formal guarantees.
Accuracy vs. Latency vs. Power Tradeoff Analysis
Pareto analysis across accuracy, inference latency, peak current draw, and binary size for each candidate architecture and compression configuration — results linking engineering tradeoffs to product-level requirements.
Data Collection & Annotation Strategy
Data collection protocols capturing the deployment distribution, annotation guidelines minimizing inter-annotator disagreement, quality control on annotation consistency, and active learning to maximize yield from limited annotation budgets.
How We Work
ML Feasibility & Problem Framing
Problem structure, data availability, and achievable performance within target hardware constraints are assessed before modeling begins — success criteria tied to product outcomes, not accuracy metrics alone. This prevents the most expensive ML mistake: building a model that cannot deploy on the target device.
Dataset Curation & Pipeline Construction
Data collection covers the full deployment distribution including edge cases and failure modes; DVC versioning, validation checks, and augmentation pipelines are implemented. Annotation guidelines and inter-annotator agreement metrics are established before labeling begins to prevent distribution shift.
Model Architecture Selection & Baseline Training
Architecture selection is driven by target device operator support, memory hierarchy, and compute primitives — not benchmark rankings — using MobileNetV3 or lightweight custom architectures for MCU targets and YOLOv8/v9 for GPU-class edge hardware. Baseline training establishes the accuracy ceiling before optimization.
Model Optimization & Hardware Validation
Per-channel INT8 PTQ is applied first with accuracy validated against full-precision baseline; QAT with fake quantization nodes targets sensitive layers when loss exceeds the threshold. Each step is benchmarked on real target hardware — latency, not theoretical FLOPs — with the accuracy/latency/power curve documented throughout.
Integration & System-Level Testing
Isolation accuracy degrades when real sensor data and pre/post-processing pipelines run together on target hardware. Numerical consistency between training and inference preprocessing is validated, post-processing latency confirmed against budgets, and corrupted inputs, sensor dropouts, and out-of-distribution samples tested for graceful handling.
MLOps Deployment & Monitoring Setup
Model registry, inference monitoring with drift detection, automated retraining triggers, and OTA model delivery through existing firmware infrastructure are configured before handoff. Monitoring dashboards and model refresh runbooks are delivered to the operations team at deployment.
Where Hardware Constraints Shape Every ML Decision
Quantization: INT8 and INT4 Without Accuracy Collapse
Batch normalization outputs, sigmoid heads, and first/last layers collapse under naive PTQ. Per-layer sensitivity analysis identifies the most harmful layers; those are excluded or promoted in a mixed-precision scheme, and QAT with fake quantization nodes is applied when PTQ alone cannot meet the accuracy threshold on Ethos-U85 or Qualcomm AI Engine.
Edge Data PipelinesYOLOv8/v9 and RT-DETR: Selecting the Right Detection Architecture for Edge Hardware
YOLOv8n/s quantize to INT8 at 30+ FPS on Hailo-8 or Jetson Nano where RT-DETR is too compute-heavy; YOLOv9's PGI mechanism delivers better accuracy at equivalent parameter counts; RT-DETR eliminates NMS variability and suits Jetson Orin with TensorRT. All candidates are benchmarked on target hardware before selection.
Computer VisionMLOps for Embedded: Model Drift, Retraining Triggers, and OTA Updates
A corrupted model binary on a remote industrial sensor is a service call — embedded MLOps requires constraints cloud MLOps ignores. Confidence distributions stream through the existing telemetry channel; KS-test drift detection triggers retraining; new models are delivered as signed delta-compressed OTA patches with automatic rollback on validation failure.
OTA Firmware
From training pipeline to deployed model on silicon — we own the full ML stack.
AI/ML Development Across Ankh's Product Range
Machine learning delivers highest value when deployed on the hardware closest to the data source — Ankh integrates ML capabilities from microcontroller-class wearables to GPU-accelerated vision systems.
AI Vision Systems
YOLOv8/v9 object detection and semantic segmentation on Hailo-8 and NVIDIA Jetson Orin at 60+ FPS
View ProductMedical Devices
FDA SaMD classification pathway for ML-enabled diagnostic features with locked algorithm documentation
View ProductIndustrial Equipment Monitoring
LSTM and Transformer anomaly detection on vibration and current signature time-series for predictive maintenance
View ProductWearable Electronics
On-device gesture and activity recognition with CMSIS-NN INT8 inference on Cortex-M33 at under 1 mW
View ProductCold Chain Monitoring
Autoencoder-based spoilage prediction from multi-sensor time series with federated learning for privacy preservation
View ProductStructural Monitoring
Vibration mode decomposition and fatigue accumulation prediction using physics-informed neural networks
View ProductRuggedized Devices
Fault classification from CAN bus and sensor fusion data under intermittent connectivity with on-device inference fallback
View ProductData Loggers
Intelligent duty-cycle control using on-device classification to capture events of interest while minimizing power consumption
View ProductPOS & Kiosk Hardware
Liveness detection and face anti-spoofing for biometric authentication using MobileNetV3 on embedded GPU
View ProductPower Monitoring
Non-intrusive load monitoring (NILM) using CNN classifiers on current waveform harmonics for appliance disaggregation
View ProductHardware-Aware ML From Day One
Unsupported NPU operators and models that barely fit in SRAM are deployment blockers found too late when accuracy drives architecture. ML engineers work alongside embedded hardware and firmware engineers from kickoff — memory budgets, operator support matrices, and SDK limitations shape architecture before the first training run.
Full-Stack Coverage from Data to OTA
Data engineering, ML modeling, embedded software, and MLOps are rarely found in a single team but all required for a successful ML hardware product. All four are covered — annotation pipeline, model training and optimization, embedded integration, and MLOps infrastructure for post-deployment maintenance.
Production Deployments, Not Research Projects
Production ML must sustain reliable behavior over a multi-year lifetime under real-world data drift. Every model ships with a model card documenting training data provenance, known failure modes, and the conditions under which it degrades gracefully.
Deliverables
Trained & Optimized Model Files
TFLite, ONNX, TensorRT, Hailo HEF, or Coral .tflite — both full-precision training checkpoint and optimized deployment binary.
Training Pipeline Codebase
PyTorch or TensorFlow codebase: data loading, augmentation, architecture, training loop, evaluation harness, and quantization scripts — reproducible from documented dataset version and hyperparameters.
Dataset & Annotation Package
Versioned dataset with COCO JSON, YOLO TXT, or CSV annotation files, data collection protocol, annotation guidelines, inter-annotator agreement metrics, and DVC-tracked history.
Hardware Benchmark Report
Inference latency (mean, p95, p99), peak SRAM, binary size, energy per inference, and validation accuracy — with comparison across all evaluated optimization configurations.
Embedded Inference Integration Code
C/C++ or Python inference integration for TFLite Micro, ONNX Runtime, TensorRT, or Hailo SDK — pre/post-processing pipelines, error handling, and timing instrumentation.
MLOps Pipeline & Monitoring Infrastructure
Model registry, drift detection dashboards, automated retraining triggers, CI/CD evaluation gating, and operational runbook for the model refresh cycle.
Model Card & Architecture Documentation
Intended use, training data provenance, evaluation methodology, performance by class and subset, known failure modes, and monitoring and retraining recommendations.
Accuracy vs. Latency Tradeoff Analysis
Pareto analysis of the accuracy/latency/power/size tradeoff surface, with recommendation linking the selected configuration to product hardware constraints.
Ankh delivers trained, optimized, and deployed ML systems with complete documentation covering data provenance, architecture rationale, optimization methodology, and operational procedures for ongoing model maintenance.
Often Paired With AI/ML Development
Computer Vision
Computer vision deployments combine the full ML stack with camera selection, ISP tuning, and optical system design for the specific sensing application.
ExploreEdge Data Pipelines
Edge ML inference requires robust data pipelines for sensor ingestion, pre-processing, feature extraction, and results telemetry.
ExploreFirmware Development
Integrating ML inference into an RTOS application requires task scheduling, DMA buffer management, and power state coordination across firmware and ML runtime.
ExploreOTA Firmware
Model updates in the field use the same OTA infrastructure as firmware, with model-specific payload packaging, integrity verification, and automatic rollback.
ExploreWork That Demonstrates the Standard
Industrial Vision System: 99.2% Weld Defect Detection at 45 FPS on Hailo-8
Ankh trained a custom YOLOv8m on 12,000 annotated weld images; INT8 PTQ achieved 99.2% recall at 0.1% false-positive rate, compiled to Hailo HEF at 45 FPS and 28 ms end-to-end latency. An MLOps pipeline monitors daily false-positive rate and triggers retraining when the rate trends upward.
Read the Case StudyWearable Health Monitor: On-Device Arrhythmia Detection Under 800 µW
Ankh developed a 1D-CNN with depthwise-separable convolutions, knowledge distillation, and INT8 QAT with CMSIS-NN-compatible layouts — 93.7% sensitivity and 97.1% specificity at 780 µW meeting IEC 60601-2-47 targets, delivered with a complete model card for FDA 510(k) submission.
Read the Case StudyReady to Put Intelligence Inside Your Hardware?From training data to deployed model on silicon.
Ankh's team has solved hard ML problems on 256 KB of SRAM at 10 mW — start with a technical feasibility assessment to define what is achievable within your hardware constraints.