ELECTRONICS DESIGNPCB LAYOUT &SIGNAL INTEGRITY
From schematic to Gerber — designed for signal integrity, EMC compliance, and first-time manufacturing success.
Ankh treats signal integrity, power delivery, and EMC as first-order design disciplines from the first component placed — not as fixes applied after a pre-compliance test failure. Every board we design is delivered with a complete fabrication package: Gerbers, drill files, assembly drawings, BOM with approved alternates, signal integrity verification report, EMC pre-compliance review, and DFM sign-off against the target fabricator's process.
What We Design
High-Speed Digital PCB
DDR4/5, PCIe Gen3/4, USB 3.x, HDMI 2.x, Ethernet GigE — fly-by topology, IBIS simulation, post-layout eye diagram verification
Mixed-Signal & Analogue
24-bit ADC front ends, sensor conditioning, precision measurement, analogue ground plane management, Kelvin-sense layout
RF & Wireless PCB
50Ω microstrip and stripline, antenna keepout, BLE/Wi-Fi/cellular co-design, filter and matching network layout, ground via fence
Power Electronics
SMPS topology selection and layout, motor driver, BMS, high-current trace sizing, PDN design, decoupling placement for target impedance
Embedded Processor & MCU
STM32, Nordic nRF, ESP32, ARM Cortex-A SoM carrier boards — high-density BGA escape, DDR routing, power sequencing
Rigid-Flex & HDI
Flex PCB, rigid-flex multi-board assembly, HDI microvias, blind and buried vias, advanced packaging for miniaturised products
FPGA & High-Density Logic
Xilinx, Intel/Altera routing, SERDES lane constraints, LVDS, GTX/GTH transceivers, high-pin-count BGA escape routing
Safety-Critical & Medical
IEC 60601-1 creepage and clearance at mains-to-SELV isolation boundary, IPC-A-610 Class 3, medical device PCB workmanship and inspection
Industrial & Ruggedised
Wide temperature from -40°C to +85°C, conformal coating design rules, MIL-spec connector interface, vibration and shock qualification design
Consumer & IoT
Cost-optimised BOM, compact form factor, antenna integration, BLE + Wi-Fi + cellular co-design, FCC/CE pre-compliance design review
How We Work
Requirements & Architecture Review
We review the functional specification, platform, regulatory constraints, form factor, and cost target before any component is selected. If the architecture has a flaw, catching it here costs a conversation — catching it at prototype costs a board spin.
Schematic Design & Component Selection
Schematic capture with parallel BOM validation: every component checked for availability, lifecycle status, and approved second source before the design is locked. Derating analysis and reference design review where the application note differs from target conditions.
Signal Integrity Pre-Layout Analysis
IBIS or S-parameter simulation before layout for any high-speed or RF design. Topology modelling, impedance budgeting, and crosstalk analysis at schematic stage — layout constraints defined before the router opens, not discovered after.
PCB Layout
Layer stack-up first. Placement driven by signal integrity, thermal, and mechanical constraints. Controlled impedance routing, differential pair management, PDN decoupling, and DFM compliance enforced throughout — not at post-layout review.
Design Review & Pre-Compliance
Post-layout signal integrity verification, EMC design review against target regulatory limits, thermal analysis at maximum ambient, and DFM review against fabricator process capabilities — all completed before Gerbers are released.
Fabrication Release & Build Support
Complete fabrication package: Gerbers, drill files, assembly drawings, BOM, and IPC-2581. Build support through first-article fabrication including component substitution management and assembly house query resolution.
Signal Integrity, EMC & Thermal — Our Engineering Standards
Signal Integrity
Impedance discontinuities and broken return paths cause reflections, crosstalk, and radiated emission — problems that cannot be fixed after the board is laid out. Ankh runs IBIS simulation before layout begins and verifies controlled impedance, differential pair matching, and eye margin before the fabrication package is released.
Signal Integrity EngineeringEMC Design
Emissions failures are a schematic and layout problem, not a test problem — filter placement, return path continuity, cable entry design, and ground via fencing are all decisions made before the first trace is routed. Ankh's pre-compliance review identifies FCC/CE risk before the prototype build, when the fix is a Gerber change rather than a retest after rework.
Regulatory Certification SupportThermal Design
Every 10°C reduction in junction temperature approximately halves the silicon failure rate — making thermal design a reliability discipline, not an afterthought. Ankh's thermal analysis identifies the highest-risk components and the most effective interventions before layout is finalised: copper pour, thermal via arrays, heatsink and TIM selection, and conduction-cooled enclosure design.
Power Systems Design
From schematic to Gerber — designed for signal integrity, EMC compliance, and first-time manufacturing success.
Electronics Design Across Ankh's Product Range
Electronics design is exercised across every product Ankh builds — each category presenting a characteristic layout challenge that determines whether the first prototype validates the design.
Wearable Electronics
Antenna detuning from human tissue proximity and minimum-footprint RF front-end design at 2.4GHz and sub-1GHz
View ProductMedical Devices
IEC 60601-1 creepage and clearance at the mains-to-SELV isolation boundary with 8mm comparative tracking index
View ProductCold Chain Monitoring
SHA-256 hash-chained flash write architecture with power-loss journal and capacitor-backed hold-up circuit
View ProductStructural Monitoring
Sub-µg/√Hz noise floor MEMS signal conditioning with GPS PPS hardware timestamp capture below 100ns
View ProductIndustrial Equipment Monitoring
HART 7 FSK physical layer and Modbus RTU at RS-485 bus multipoint topology with 120Ω line termination
View ProductAI Vision Systems
CoaXPress CXP-12 camera interface at 12.5Gbps with FPGA image pre-processing pipeline and GigE Vision output
View ProductPOS & Kiosk Hardware
PCI PTS tamper-detection mesh routing on inner PCB layers at sub-0.5mm pitch with volatile key memory backup
View ProductWireless Communication
PA harmonic filter design for FCC Part 90 spurious emission compliance at -36dBm above 1GHz carrier
View ProductData Loggers
24-bit sigma-delta simultaneous multi-channel ADC with documented anti-aliasing filter at or below Nyquist
View ProductRuggedized Devices
IPC-A-610 Class 3 workmanship with 100% AOI, X-ray inspection for BGA, and conformal coating SIR test
View ProductSmart Home Automation
Matter DCL attestation certificate provisioned at manufacturing with unique device identity and CSA-approved PAA
View ProductPower Monitoring
CT saturation modelling for high-harmonic industrial loads and IEC 61000-4-30 Class A measurement accuracy
View ProductSignal Integrity Is a First-Order Design Input, Not a Post-Layout Review
Signal integrity work done before layout — IBIS simulation, transmission line modelling, impedance budget, crosstalk analysis — constrains the layout correctly from the first trace placed. Ankh begins every design with signal integrity analysis at the schematic stage and uses the output as layout constraints, not as post-layout findings that require a board spin to address.
DFM Is Designed In, Not Inspected In
A PCB layout that ignores the target fabricator's copper-to-edge distance, paste aperture requirements, or via-in-pad fill capabilities will require Gerber rework and days of schedule delay. Ankh designs for the specific fabricator's process from the first placement: stack-up defined before layout begins, DFM rules loaded as tool constraints, DFM review completed as a pre-release check.
The BOM Is as Important as the Schematic
A component on 52-week lead time with no approved second source is a production risk, not an engineering design. Ankh validates availability, lead time, lifecycle status, and approved alternates for every BOM line item during schematic design — before layout begins, not after the prototype is built and the design is locked.
Deliverables
Schematic Package
Hierarchical schematic in native EDA format (KiCad, Altium), PDF for review, and design review report with component derating and worst-case circuit analysis
Bill of Materials
Fully specified BOM with manufacturer part number, approved alternate, real-time distributor stock check, component lifecycle status, and unit cost at prototype quantity and production volume
PCB Layout
Native EDA layout file, reference designator placement drawing, and PCB assembly drawing with component orientation and polarity callouts
Fabrication Package
Gerber 274X with all copper, mask, paste, and silk layers; NC drill files in Excellon format; drill drawing; board outline DXF; IPC-2581 neutral format
Signal Integrity Report
IBIS simulation results for critical interfaces, post-layout impedance extraction, differential pair matching verification, and eye diagram estimation for critical serial links
EMC Pre-Compliance Report
Conducted and radiated emissions risk assessment against target regulatory limits (FCC Part 15B, CISPR 32, EN 55032), layout EMC review findings, and recommended modifications before prototype build
Thermal Analysis
Junction temperature predictions at maximum ambient, copper pour and thermal via recommendations, heatsink and TIM specification, and sealed enclosure thermal resistance calculation
DFM Report
Fabricator-specific DFM compliance review covering minimum features, paste aperture, via-in-pad, assembly drawing, and panelisation with tooling strip and fiducial placement
Deliverable scope varies by engagement. Ankh tailors the package to the programme requirement — from full-stack schematic-to-Gerber delivery to targeted signal integrity analysis on a specific interface.
Often Paired With Electronics Design
Embedded Firmware Development
Hardware bring-up, driver development, and production firmware written alongside the PCB design — ready when the first boards arrive.
ExploreRF & Wireless Engineering
Antenna design and matching, RF link budget, co-existence analysis, and regulatory RF testing for Wi-Fi, BLE, cellular, and custom band designs.
ExplorePower Systems & Battery Design
SMPS topology selection, switching regulator design, battery management, and PDN design for battery-powered and mains-connected products.
ExploreRegulatory Certification Support
FCC, CE, UKCA, and UL certification support — pre-compliance planning, test house engagement, and design modification from first test to approval.
ExploreWork That Demonstrates the Standard
16-Layer DDR5 SoM Carrier Board for an Edge AI Platform
16-layer rigid carrier for a Qualcomm SA8295P SoM with 128-bit LPDDR5 at 6400MT/s — fly-by topology with matched stubs below 5mil, 90Ω differential impedance to ±8%, IBIS simulation of SSO ground bounce, and pre-compliance EMC review identifying two clock routing changes before prototype build. DDR5 passed first-article functional test at full data rate across -40°C to +85°C.
Read the Case Study4-Layer Mixed-Signal Data Acquisition PCB for Industrial Measurement
4-layer PCB for a 24-bit simultaneous 16-channel sigma-delta ADC system — analogue ground plane island with single-point AGND connection, 4th-order Butterworth anti-aliasing at 2.4kHz, precision reference with Kelvin-sense and guard ring, and strain gauge signal conditioning at 0.1µV/°C input offset drift. DFM completed before first Gerber release: zero fabrication queries and zero board spins for design-related failures.
Read the Case StudyReady to design your next PCB?Let's build it right the first time.
Signal integrity as a first-order design input. DFM designed in from the first placement. A BOM validated for availability before layout begins. Full fabrication package on delivery.